An Empirical Study of the Performance of a Simulated Multithreaded Processor

Processor Martin T. Rowland and Randall A. Helzerman Intel Corporation, Design Technologies 2111 N.E. 25th Avenue JF1-71 Hillsboro, OR 97124-5961 August 23, 1995 Abstract Because dependencies limit the amount of parallelism in an instruction stream, a VLIW or superscalar processor typically cannot execute as many instructions each cycle as it has functional units. This otherwise wasted processing power can be harnessed in a multithreaded architecture, which exploits the independence of instructions from separate processes. If a multithreaded processor nds that the current process can not use a functional unit, it looks for an instruction from another ready process which can.This paper presents the results of an empirical study that measures the e ectiveness on throughput of multithreaded processing when applied to a super scalar architecture.